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Lockheed Martin Develops Configurable, Space-Qualified Digital Channelizer using MathWorks™ Tools

With Simulink® and EDA Simulator Link™ MQ, simulation and verification are performed in one environment. As a result, we can test the design from end to end, improving quality and ensuring design accuracy and validity." - Bradford Watson, Lockheed Martin Space
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Harris Accelerates Verification of Signal Processing FPGAs

"EDA Simulator Link enabled us to greatly reduce functional verification development time by providing a direct cosimulation interface between our MATLAB model and our logic simulator. As a result, we verified our design earlier, identified problems faster, completed more tests, and compressed our entire development cycle." - Jason Plew, Harris Corporation
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EDA Simulator Link

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Verify VHDL and Verilog using HDL simulators and FPGAs

eda-simulator-link edasimlink fig1 wl 20105
Elaboration of a floating-point reference algorithm and verification of a Verilog implementation using a cosimulation interface.

EDA Simulator Link™ provides a verification interface between MATLAB® or Simulink® and your HDL simulator or FPGA board. Using EDA Simulator Link you can verify a Verilog® or VHDL® design against your Simulink model or MATLAB algorithm using cosimulation with a Verilog or VHDL simulator, such as Mentor Graphics® ModelSim® or Cadence® Incisive®. EDA Simulator Link also lets you perform hardware verification on your FPGA board using FPGA-in-the-loop simulation.

With EDA Simulator Link you can use MATLAB code and Simulink models as a test bench that generates stimulus for an HDL design and analyzes the simulation's response. You can replace HDL design components with MATLAB code and Simulink models, enabling simulation of the complete system before all the HDL design elements are available.

EDA Simulator Link lets you create transaction-level model (TLM) components for use in virtual prototyping environments.

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